/*
 * soft_serial_stm32f103ze.h
 *
 * Change Logs:
 * Date           Author        Notes
 * 2021-09-29     qiyongzhong   create v1.0
 */

#ifndef __SOFT_SERIAL_STM32F103ZE_H__
#define __SOFT_SERIAL_STM32F103ZE_H__

#ifdef CHIP_NAME_STM32F103ZE

#define SS_MODE_HALF    //half-duplex mode, rx channel and tx channel may is same

#define SS_SCOM_CFG_TABLE \
{\
    {"scom1",  {TIM1, LL_TIM_CHANNEL_CH1, GPIOE, GPIO_PIN_9 }, {TIM1, LL_TIM_CHANNEL_CH1, GPIOE, GPIO_PIN_8 }},\
    {"scom2",  {TIM1, LL_TIM_CHANNEL_CH2, GPIOE, GPIO_PIN_11}, {TIM1, LL_TIM_CHANNEL_CH2, GPIOE, GPIO_PIN_10}},\
    {"scom3",  {TIM1, LL_TIM_CHANNEL_CH3, GPIOE, GPIO_PIN_13}, {TIM1, LL_TIM_CHANNEL_CH3, GPIOE, GPIO_PIN_12}},\
    {"scom4",  {TIM1, LL_TIM_CHANNEL_CH4, GPIOE, GPIO_PIN_14}, {TIM1, LL_TIM_CHANNEL_CH4, GPIOE, GPIO_PIN_15}},\
    {"scom5",  {TIM2, LL_TIM_CHANNEL_CH1, GPIOA, GPIO_PIN_15}, {TIM2, LL_TIM_CHANNEL_CH1, GPIOA, GPIO_PIN_12}},\
    {"scom6",  {TIM2, LL_TIM_CHANNEL_CH2, GPIOB, GPIO_PIN_3 }, {TIM2, LL_TIM_CHANNEL_CH2, GPIOB, GPIO_PIN_4 }},\
    {"scom7",  {TIM2, LL_TIM_CHANNEL_CH3, GPIOB, GPIO_PIN_10}, {TIM2, LL_TIM_CHANNEL_CH3, GPIOB, GPIO_PIN_12}},\
    {"scom8",  {TIM2, LL_TIM_CHANNEL_CH4, GPIOB, GPIO_PIN_11}, {TIM2, LL_TIM_CHANNEL_CH4, GPIOB, GPIO_PIN_13}},\
    {"scom9",  {TIM3, LL_TIM_CHANNEL_CH1, GPIOA, GPIO_PIN_6 }, {TIM3, LL_TIM_CHANNEL_CH1, GPIOA, GPIO_PIN_4 }},\
    {"scom10", {TIM3, LL_TIM_CHANNEL_CH2, GPIOA, GPIO_PIN_7 }, {TIM3, LL_TIM_CHANNEL_CH2, GPIOA, GPIO_PIN_5 }},\
    {"scom11", {TIM3, LL_TIM_CHANNEL_CH3, GPIOB, GPIO_PIN_0 }, {TIM3, LL_TIM_CHANNEL_CH3, GPIOC, GPIO_PIN_4 }},\
    {"scom12", {TIM3, LL_TIM_CHANNEL_CH4, GPIOB, GPIO_PIN_1 }, {TIM3, LL_TIM_CHANNEL_CH4, GPIOC, GPIO_PIN_5 }},\
    {"scom13", {TIM4, LL_TIM_CHANNEL_CH1, GPIOD, GPIO_PIN_12}, {TIM4, LL_TIM_CHANNEL_CH1, GPIOD, GPIO_PIN_10}},\
    {"scom14", {TIM4, LL_TIM_CHANNEL_CH2, GPIOD, GPIO_PIN_13}, {TIM4, LL_TIM_CHANNEL_CH2, GPIOD, GPIO_PIN_11}},\
    {"scom15", {TIM4, LL_TIM_CHANNEL_CH3, GPIOD, GPIO_PIN_14}, {TIM4, LL_TIM_CHANNEL_CH3, GPIOG, GPIO_PIN_2 }},\
    {"scom16", {TIM4, LL_TIM_CHANNEL_CH4, GPIOD, GPIO_PIN_15}, {TIM4, LL_TIM_CHANNEL_CH4, GPIOG, GPIO_PIN_3 }},\
    {"scom17", {TIM5, LL_TIM_CHANNEL_CH1, GPIOA, GPIO_PIN_0 }, {TIM5, LL_TIM_CHANNEL_CH1, GPIOC, GPIO_PIN_0 }},\
    {"scom18", {TIM5, LL_TIM_CHANNEL_CH2, GPIOA, GPIO_PIN_1 }, {TIM5, LL_TIM_CHANNEL_CH2, GPIOC, GPIO_PIN_1 }},\
    {"scom19", {TIM5, LL_TIM_CHANNEL_CH3, GPIOA, GPIO_PIN_2 }, {TIM5, LL_TIM_CHANNEL_CH3, GPIOC, GPIO_PIN_2 }},\
    {"scom20", {TIM5, LL_TIM_CHANNEL_CH4, GPIOA, GPIO_PIN_3 }, {TIM5, LL_TIM_CHANNEL_CH4, GPIOC, GPIO_PIN_3 }},\
}

#define SS_TIM_CH_REMAP()  do{ \
    __HAL_AFIO_REMAP_TIM1_ENABLE();     \
    __HAL_AFIO_REMAP_TIM2_ENABLE();     \
    __HAL_AFIO_REMAP_TIM3_DISABLE();    \
    __HAL_AFIO_REMAP_TIM4_ENABLE();     \
    __HAL_AFIO_REMAP_TIM5CH4_DISABLE(); \
}while(0)

#define SS_USING_TIM1
#define SS_USING_TIM2
#define SS_USING_TIM3
#define SS_USING_TIM4
#define SS_USING_TIM5
//#define SS_USING_TIM8

#endif
#endif

